1. Field of the Invention
Embodiments of the present invention relate to methods of forming a semiconductor package formed on a substrate plated with conductive material only on a single side.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices. These devices include for example digital music players, cellular phones, handheld PCs, digital cameras, digital video camcorders, smart phones, car navigation systems and electronic books.
Flash memory storage cards come in a number of different configurations, but generally include a semiconductor package housed within a standard sized and shaped enclosure. These standard enclosures include SD (Secure Digital) cards, a Compact Flash, a Smart Media, a Mini SD Card, an MMC, an xD Card, a Transflash memory card or a Memory Stick. The semiconductor package used in such memory devices includes an integrated circuit typically having passive components, one or more memory chips and, in some configurations, a controller chip mounted on and electrically connected to a substrate. Substrates on which the integrated circuit may be formed include printed circuit boards, leadframes and polyimide tapes. Once formed on the substrate, these integrated circuits are typically encapsulated in a molding compound which protects the integrated circuit and removes heat from the package.
Where once memory devices included a plurality of discrete semiconductor packages, each handling different functions, currently a plurality of integrated circuit components may be packaged together to provide a complete electronic system in a single package. For example, multichip modules (“MCM”) typically include a plurality of chips mounted side by side on a substrate and then packaged. Another example is a system-in-a-package (“SiP”), where a plurality of chips may be stacked on a substrate and then packaged.
A conventional, two-sided semiconductor package 20 is shown (without encapsulation) in prior art FIGS. 1 and 2. Package 20 may be a land grid array (LGA) package, including a substrate 22 on which are mounted a pair of semiconductor die 24 (shown only in outline in FIG. 1). The substrate 22 may in general include a dielectric core 26 having conductive layers 28 and 30 formed on its top and bottom surfaces. A conductance pattern of electrical traces may be defined in one or both conductive layers. Through-holes, or vias, 32 are formed through the substrate, and plated to allow electrical communication between the conductance patterns on the top and bottom surfaces of the substrate. Bond pads 34 may be provided on the substrate 22 to which wire bonds 36 (seen in FIG. 2) may be ultrasonically welded to electrically couple the die 24 to the substrate 22. Contact fingers 38 may also be provided on substrate 22 for mating with similar contacts on a host device into which package 20 may be inserted. The contact fingers 38 are located on a side of the substrate opposite the die 24 and bond pads 34. Consequently, LGA packages have conductive layers and plating on both sides of the substrate as shown.
The copper of the conductive layers 28 and 30 provides a generally poor bonding surface for welding the wire bonds 36 to the bond pads 34. Copper also provides a poor surface for withstanding the repeated engagements undergone by the contact fingers 38. It is therefore known to plate the bond pads and contact fingers with, for example, gold or nickel/gold (Ni/Au) plating.
A double-sided substrate (i.e., one having a conductive layer on both its top and bottom surfaces as shown in FIG. 2) is a relatively costly structure to manufacture. A previous approach to overcome this problem was to stack a maximum number of die on the double-sided substrate. However, present package dimensions and bond pad positioning has made it difficult to further increase the number of die which may be stacked on a substrate. It would therefore be advantageous to find another method for overcoming the high cost of substrate fabrication.
It is known to provide a finished substrate with a single-sided substrate. However, often the substrate is a conventional substrate in which one of the layers has been etched away. For example, United States Patent Application Publication No. 2001/0000156, entitled, “Package Board Structure and Manufacturing Method Thereof,” discloses a semiconductor package which, in its assembled state, includes a single-sided substrate. However, the package starts with a laminate core having a copper film on the top and bottom surfaces. During fabrication, one of the copper layers is etched away.
U.S. Pat. No. 6,190,943, entitled, “Chip-Scale Packaging Method,” ('943 patent) discloses a chip scale package having a single-sided substrate. However, unlike LGA packages, chip scale packages such as disclosed in the '943 patent, do not require electrical connections to be made from top and bottom surfaces of the substrate. All electrical connections may be established from only the top or bottom side of the substrate.